Euresys Vision Standard IP Cores - Multipix Imaging
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Euresys Vision Standard IP Cores

Vision Standard IP Cores from the Sensor to Image division of Euresys:

  • Compatible with Xilinx 7 Series (and up) and Intel/Altera Cyclone V devices (and up)
  • Compact, customisable
  • Delivered with a working reference design

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Vision Standard IP Cores for streamlining sensor development

Euresys Sensor To Image


Working Reference Design

Sensor to Image (S2I) are a subdivision of Euresys who specialise in IP cores. Their Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. They minimise development time and allow for top-notch performance with a small footprint as well as leaving enough flexibility to customise the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.


Top Level Design

The first component of the IP Core is the Top Level Design. It is an interface between external hardware (imager, sensors, GigE VisionUSB3 Vision or CXP Vision PHY) and FPGA internal data processing. We deliver this module as VHDL source code that can be adapted to custom hardware.


Video Acquisition Module

The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code, which has to be replaced by a sensor interface and pixel processing logic in the camera design.


FPGA Integrated CPU

An FPGA integrated CPU (MicroBlaze, NIOS, ARM) is used for several non-time-critical control and configuration tasks on the Vision Standard IP Cores. This software is written in C and can be extended by the customer.


MVDK Machine Vision Development Kit

Sensor to Image MVDK development kit is a flexible evaluation platform for machine vision applications. With support for CoaXPress, GigE Vision and  USb3 host/device reference designs.

The kit also features support for Sony IMX imager interface designs and various Enclustra FPGA modules with Intel or Xilinx FPGAs.